How System-level Design Explorer works?
Anew’s product - System-Level Design Explorer's solution is:
System-Level Design Explorer product takes a set of user inputs (constraints) such as required:
Minimum Mean-Time Between Failures (MTBF) - For Enhanced Reliability
Minimum number of years on parts availability - For Supply-Chain Integrity
Future incremental functionality (Specification) - How much more Re-configurable fabrics, Memory, FPGA LUTs, and FPAA analog circuits to the baseline design? - For Specification Evolvability
Minimum latency and maximum throughput - For Performance
Minimal Power both dynamic and static - For Power
Minimal cost for the build-of-materials (parts) - Build of Materials
Explores all possible solutions against available parts that meets the above user inputs leveraging technologies such as:
Re-configurable computing fabrics
Memories
FPGA LUTs
FPAAs
Dynamic Reconfiguration of RTOS and Embedded Software
Artificial Intelligence (AI), Machine Learning (ML) and Big-Data
To arrive at one of more designs for the software and hardware and writes out the hardware design in EDIF.
Below is the system architecture of System-level
Design Explorer that supports the Bottom-Up Flow
(BUF) and the Top-down Flow (TDF):
